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| Ordering number : EN*5237 CMOS LSI LC8905V Digital Audio Interface Receiver Preliminary Overview The LC8905V is for use in IEC 958 and EIAJ CP-1201 format data transmission between digital audio equipment. This LSI is used on the receiving side, and handles synchronization with the input signal and demodulation of that signal to a normal format signal. Package Dimensions unit: mm 3175A-SSOP24 [LC8905V] Features * On-chip PLL circuit synchronizes with the transmitted IEC 958 and EIAJ CP-1201 format signal. * Provides 128fs, bit, and L/R clock outputs. * System clock can be selected to be either 384fs or 512fs. * Microprocessor interface code settings for different output types -- Input pin, emphasis output, input bi-phase data output, and validity flag output settings -- Audio data output format setting -- Channel status output (32-bit output for consumer products) -- Subcode Q output with CRC flags (80 bits) * Start ID and shortening ID detection for DAT (Digital Audio Tape recorder) that use subcodes * CMOS, single-voltage power supply * Miniature package: SSOP-24 SANYO: SSOP24 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN D3095HA (OT) No. 5237-1/16 LC8905V Pin Assignment Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol DIN1 DIN2 E/DOUT VDD R VIN VCO GND CKSEL XMODE AVOCK TST1 TST2 SCLK/CL XLAT/CE SWDT/DI SRDT/DO DQSY/LD CKOUT FS128 BCK LRCK DATAOUT ERROR I I I I I I I I O O O O O O O O I I O I/O I I O Description Data input with built-in amplifier (for coaxial or optical module input) Data input (for optical module input) Emphasis, input bi-phase, and validity flag output Power supply VCO gain control input VCO free-running setting input PLL low-pass filter setting Ground System clock selection input (384fs or 512fs) Reset input PLL error lock avoidance clock input Test input (Must be connected to ground in normal operation) Test input (Must be connected to ground in normal operation) Microprocessor interface clock input Microprocessor interface latch/chip enable input Microprocessor interface write data input Microprocessor interface read data output Microprocessor interface subcode Q and ID synchronization output VCO clock output (free running, 384fs, or 512fs) 128fs clock output Bit clock output L/R clock output (left channel = high, right channel = low) Audio data output PLL lock error mute output No. 5237-2/16 LC8905V Block Diagram No. 5237-3/16 LC8905V Specifications Absolute Maximum Ratings at Ta = 25C Parameter Maximum supply voltage Maximum I/O voltages Operating temperature Storage temperature Symbol VDD max VI VO max Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -30 to +75 -55 to +125 Unit V V C C Allowable Operating Ranges Parameter Supply voltage Symbol VDD Conditions min 4.5 typ 5.0 max 5.5 Unit V Electrical Characteristics DC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V, VSS = 0 V Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Current drain Input amplitude Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH VOL IDD Vpp Conditions Applies to the DIN2 pin. TTL levels Applies to the DIN2 pin. TTL levels Applies to the CKSEL, AVOCK, TST1, and TST2 pins. CMOS levels Applies to the CKSEL, AVOCK, TST1, and TST2 pins. CMOS levels Applies to the XMODE, SCLK/CL, XLAT/CE, SWDT/DI pins. CMOS Schmitt inputs Applies to the XMODE, SCLK/CL, XLAT/CE, SWDT/DI pins. CMOS Schmitt inputs IOH = -1 A IOL = 1 A VDD = 5.0 V, Ta = 25C, input data fs = 48 kHz Measured before the DIN1 pin input capacitor. 0.4 10 min 2.2 -0.3 0.7 VDD -0.3 0.8 VDD -0.3 VDD - 0.05 VDD + 0.05 15 VDD + 0.3 typ max VDD + 0.3 +0.8 VDD + 0.3 0.3 VDD VDD + 0.3 0.2 VDD Unit V V V V V V V V mA V AC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V Parameter Input pulse width Output pulse width Output data setup time Output data hold time Output delay Symbol tWBI tWBO tDSO tDHO tBD fs = 48 kHz Conditions min 10 160 80 80 -10 0 +10 typ max Unit s ns ns ns ns No. 5237-4/16 LC8905V No. 5237-5/16 LC8905V Microprocessor Interface Block AC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V (when CKSEL is low) Parameter CL low pulse width CL high pulse width Data setup time Data hold time CE delay time CL delay time CE delay time LD pulse width Data delay time Data delay time Symbol tWL tWH tDS tDH tD3 tD4 tD5 tW tD1 tD2 fs = 44.1 kHz CL = 30 pF CL = 30 pF 136 75 75 Conditions min 100 100 50 50 1.0 50 100 typ max Unit ns ns ns ns s ns ns s ns ns Input mode Output mode No. 5237-6/16 LC8905V Microprocessor Interface Block AC Characteristics at Ta = -30 to +75C, VDD = 4.5 to 5.5 V (when CKSEL is high) Parameter CL low pulse width CL high pulse width Data setup time Data hold time CE delay time LD pulse width Data delay time Data delay time Symbol tWL tWH tDS tDH tD tW tD1 tD2 fs = 44.1 kHz CL = 30 pF CL = 30 pF Conditions min 100 100 50 50 100 136 75 75 typ max Unit ns ns ns ns s s ns ns Input mode Output mode No. 5237-7/16 LC8905V Functions 1. Data Input and Output (DIN1, DIN2, E/DOUT) The DIN1 pin has a built-in amplifier, and can receive signals with an amplitude of about 400 mVp-p (coaxial input). The DIN2 pin is only for use with optical modules. Note that although the data input pins are controlled by the microprocessor, DIN1 can be selected when a microprocessor is not used. The microprocessor interface pins must be tied low in such applications. The E/DOUT normally outputs channel status information. However, it can be set to output either the input bi-phase data or the validity flag by command codes from the microprocessor. 2. PLL (R, VIN, VCO, AVOCK) This circuit includes a built-in VCO and supports sampling frequencies of 32, 44.1, and 48 kHz. The resistor connected to R functions as both the VCO gain control and as temperature compensation. The VIN pin sets the VCO free-running frequency. The PLL circuit can be reset within a fixed period when it operates incorrectly, for example, if a lock pull-in failure occurs, by inputting an asynchronous, continuously operating clock signal to the AVOCK pin. 3. Clock Settings and Output (FS128, BCK, LRCK, DATAOUT, CKSEL, CKOUT) A 128fs clock signal is output from the FS128 pin. Figure 1 shows the output timing for the BCK, LRCK, and DATAOUT pins. The CKOUT clock output is set by the CKSEL pin as listed in the table below. CKSEL L H CKOUT 384fs clock output 512fs clock output The microprocessor interface format is also set by CKSEL as listed in the table below. CKSEL L H Microprocessor interface Figure 2 Figure 3 No. 5237-8/16 LC8905V Figure 1 Data Output Timing No. 5237-9/16 LC8905V Figure 2 Microprocessor Interface Timing 1 No. 5237-10/16 LC8905V Figure 3 Microprocessor Interface Timing 2 No. 5237-11/16 LC8905V Microprocessor Interface (SCLK/CL, XLAT/CE, SWDT/DI, SRDT/DO, DQSY/LD) 1. Data input and output addresses are allocated as follows: Data input or output Data input C bit output Subcode Q, ID output F7 F8 F9 Figure 2: Microprocessor Interface Timing 1 B0 1 0 1 B1 1 0 0 B2 1 0 0 B3 0 1 1 A0 1 1 1 A1 1 1 1 A2 1 1 1 A3 1 1 1 EA E9 E8 Figure 3: Microprocessor Interface Timing 2 B0 0 1 0 B1 1 0 0 B2 0 0 0 B3 1 1 1 A0 0 0 0 A1 1 1 1 A2 1 1 1 A3 1 1 1 2. The input command codes control the following settings: * System stop * Data input pin settings * Input bi-phase data output selection * Validity flag output selection * Audio data output format setting DI1: Stops VCO operation and thus stops the system. DI1 System L Operating H Stopped DI2: Selects which input data to demodulate. DI2 Data demodulation input L DIN1 H DIN2 DI3 and DI4: Select the E/DOUT pin output. DI3 DI4 E/DOUT L Emphasis data output L H Validity flag output L DIN1 input data output H H DIN2 input data output DI5 and DI6: Set the audio data output format. DI5 DI6 DATAOUT L L H L 20-bit rightjustified MSB first H H 20-bit leftjustified MSB first 16-bit right- 20-bit rightjustified justified MSB first LSB first All bits are set low immediately after XMODE is switched from low to high. DI0 and DI7 are not used. No. 5237-12/16 LC8905V 3. The following output settings can be controlled: * Channel status (C bit) output * Subcode Q data output * Status ID and shortening ID detection for DAT that use subcodes C bit output * This function presumes that this IC will be used in consumer mode and thus only handles the first 32 bits. * The flag is fixed at the high level (although there is no flag in the type 1 microprocessor interface timing), and the data format is LSB first. * Error and update checking is not applied to the data. * The internal shift register is reset if a PLL lock error occurs. * An interval of at least 6 msec must be provided between consecutive data readout operations. Subcode Q output * Subcode Q can be read out after the fall of the DQSY/LD signal. Also note that the data is updated every time this signal falls. However, this signal will not be output (fall) unless 96 bits of subcode Q data (include the CRC check bits) is input. * The flag outputs a high when the CRC check passes, and low if the CRC check fails. * The bit order is LSB first within each byte of the 80 bits of subcode Q data. ID detection * The start ID and shortening ID are only detected when the DAT category code (1100000L) is received. * These IDs are detected as follows: -- A low pulse is output from DQSY/LD if a start ID (R0) or a shortening ID (L1) is detected following a sync signal (L0). -- After this signal, data can be read out from SRDT/DO by inputting the same address value as that used for subcode Q data to SWDT/DI. Figure 4 User Data for DAT that Use Subcodes * The table below shows the relationship between the sync signal (L0), the start ID (R0), the shortening ID (L1), and the data output. (L0): SYNC (R0): Start ID (L1): Shortening ID Flags + 80 data bits Detected ID H H L all H Start ID H L H all L Shortening ID * Output pins The output scheme used for SRDT/DO differs depending on the microprocessor interface format selected by CKSEL. CKSEL L H Format Figure 2 Figure 3 SRDT/DO Open-drain output Three-state output No. 5237-13/16 LC8905V Error (ERROR) The ERROR pin goes high if there is an error in the input data or if the PLL is unlocked. It holds the high level for about 200 to 300 msec after data demodulation returns to normal and then goes low. The table below lists the data processing when an error has occurred. Type of error Up to 8 consecutive parity errors Over 8 consecutive parity errors PLL lock error DATAOUT Previous data value L L C bit Output Output L Sub Q Output Output L ID Output Output L E/DOUT Output Output L System Reset (XMODE) Normal system operation is started by setting XMODE high after the power supply has risen above at least 4.5 V. If XMODE is set low, the VCO free-running oscillator clock is output from CKOUT. Setting XMODE low once again after power on resets the system. No. 5237-14/16 LC8905V Sample Application Circuit No. 5237-15/16 LC8905V s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 5237-16/16 |
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